1. Field of the Invention
The present invention relates to a static random-access-memory (SRAM) cell and, more particularly, to a five-transistor SRAM cell.
2. Description of the Related Art
A random-access-memory (RAM) cell is a semiconductor memory which stores information only as long as the power supplied to the memory cell remains uninterrupted. A static random-access-memory (SRAM) cell is a type of RAM cell that stores information in a flip-flop which is formed from a pair of cross-coupled inverters.
FIG. 1 shows a schematic diagram that illustrates a conventional SRAM cell 100. As shown in FIG. 1, cell 100 includes a flip-flop which is formed from a pair of inverters: a first inverter 110 and a second inverter 120.
First inverter 110, which includes a p-channel transistor P1 and a n-channel transistor N1, has an input connected to a node A, and an output connected to a node B. Second inverter 120, which includes a p-channel transistor P2 and a n-channel transistor N2, has an input connected to node B and an output connected to node A.
In addition, cell 100 also includes an input n-channel transistor N3 and an output n-channel transistor N4. As shown, transistor N3 is connected to an input node DATA IN, a write line WR, and node B, while transistor N4 is connected to an output node DATA OUT, a read line RD, and node A. Thus, a conventional SRAM cell requires six transistors.
In operation, data is written to cell 100 by placing either a low voltage for a logic zero or a high voltage for a logic one on the input node DATA IN. Transistor N3 is then turned on by pulsing write line WR with a high voltage.
For example, assume that cell 100 stores a logic one such that a low voltage (logic zero) is on node A and a high voltage (logic one) is on node B. The low voltage on node A turns on transistor P1 which drives a high voltage onto node B. The high voltage on node B, in turn, turns on transistor N2 which drives a low voltage onto node A.
If a logic zero is to be written to cell 100, the input node DATA IN is connected to a low voltage, such as ground, and transistor N3 is pulsed on. Turning on transistor N3 drives a low voltage onto node B which, in turn, pulls down the voltage on node B. Since transistor P1 is driving a high voltage onto node B, transistor N3 must be able to overpower transistor P1 and force a low voltage onto node B.
Once transistor N3 forces a low voltage onto node B, the low voltage turns off transistor N2 and turns on transistor P2 which drives the power supply voltage Vcc onto node A. The high voltage on node A turns off transistor P1 and turns on transistor N1, thereby driving a low voltage onto node B. The width of the pulse used to turn on transistor N3 is set to fall, and thereby turn off transistor N3, after transistor N1 has driven a low voltage onto node B, i.e., after the flop has flipped.
On the other hand, if a logic one is to be written to cell 100 (while a logic zero is on node A and a logic one is on node B), a high voltage is placed on input node DATA IN and transistor N3 is again pulsed on. In this case, however, no significant charge is transferred because a high voltage is already present on node B.
Similarly, assume that cell 100 stores a logic zero such that a high voltage (logic one) is on node A and a low voltage (logic zero) is on node B. The high voltage on node A turns on transistor N1 which drives a low voltage onto node B. The low voltage on node B, in turn, turns on transistor P2 which drives a high voltage onto node A.
If a logic zero is to be written to cell 100, the input node DATA IN is connected to ground and transistor N3 is pulsed on. As above, no significant charge is transferred because a low voltage is already present on node B.
On the other hand, if a logic one is to be written to cell 100, a high voltage, such as Vcc, is placed on input node DATA IN, and transistor N3 is turned on by pulsing write line WR with a high voltage. Turning on transistor N3 drives a high voltage onto node B which, in turn, pulls up the voltage on node B.
Since transistor N1 is driving a low voltage onto node B, transistor N3 must be able to overpower transistor N1 and force a high voltage onto node B. Once transistor N3 forces a high voltage onto node B, the high voltage turns off transistor P2 and turns on transistor N2 which, in turn, drives a low voltage onto node A.
The low voltage on node A turns off transistor N1 and turns on transistor P1, thereby driving a high voltage onto node B. As above, the width of the pulse used to turn on transistor N3 is set to fall, and thereby turn off transistor N3, after transistor P1 has driven a high voltage onto node B, i.e., after the flop has flipped.
Cell 100 is read by precharging output node DATA OUT to a high voltage, and then turning on transistor N4 by pulsing read line RD with a high voltage. If node A is high, no significant charge is transferred and cell 100 is read as having a logic zero. On the other hand, if node A is low, the output node DATA OUT is discharged through transistors N4 and N2, and cell 100 is read as having a logic one.
One of the problems with cell 100 is that, when compared to a dynamic random-access-memory (DRAM) cell which stores information as a charge on a capacitor, cell 100 consumes significantly more silicon real estate than a standard DRAM cell. Thus, there is a desire to reduce the size of a SRAM cell.
Another problem occurs when data is being written into cell 100. As noted above, when cell 100 stores a logic zero, transistor N1 is on and drives a low voltage onto node B to turn on transistor P2. To be able to write a logic one into cell 100, transistor N3 must be able to overpower transistor N1 so that transistor P2 will turn off and transistor N2 will turn on.
To overpower transistor N1, transistor N3 is typically formed to be larger than transistor N1. However, to minimize the silicon real estate consumed by cell 100, transistor N3 should not be made any larger than is necessary. (To help minimize the size of transistor N3, the trip point of inverter 120 (transistors P2/N2) is often lowered so that transistor P2 will turn off and transistor N2 will turn on when the voltage on node B is less than one-half the supply rail.)
Sizing transistor N3 to be able to overpower transistor N1 while at the same time minimizing the silicon real estate consumed by transistor N3 is not a trivial task because the charge transferred into node B via transistor N3 varies over time.
With a n-channel transistor, the overdrive of the transistor is defined as the gate-to-source voltage V.sub.GS minus the threshold voltage V.sub.TH (V.sub.GS -V.sub.TH). Thus, as the source voltage rises, the overdrive of the transistor declines.
With transistor N1, the source is connected to ground and, therefore, does not change. With transistor N3, however, the source is connected to node B and rises as the voltage on node B rises. As a result, the overdrive of transistor N3 decreases as the voltage on node B increases.
Thus, the charge transferred into node B varies over time. In addition to a rising source voltage, temperature and process variations can also effect the amount of charge that can be transferred to node B.
(Overpowering transistor P1, when transistor P1 is driving a high voltage onto node B, to write a logic zero into cell 100 is not a problem because a n-channel transistor can sink approximately twice the current that an equally-sized p-channel transistor can source.)
Thus, in addition to a smaller size, there is a need for a SRAM cell which eliminates the need for one n-channel transistor to overpower another n-channel transistor.